“00010000011001011111111111110100” is a valid 32-bit MIPS instruction binary. Assume that the value of PC for the current instruction is 128. Assume that all data memory entries are initialized to zero, and the processor’s registers have the following values at the beginning of the cycle in which the above instruction is fetched. .
|
r0 |
r1 |
r2 |
r3 |
r4 |
r5 |
r6 |
r8 |
r12 |
r31 |
|
0 |
0 |
-2 |
7 |
-4 |
7 |
9 |
-8 |
22 |
16 |
What is the MIPS assembly code corresponding to this 32-bit instruction binary?
What are the outputs of the “Sign-extend” and the “Shift left 2” units for this instruction?
What is the new PC address after this instruction is executed?
Now consider a modified MIPS processor that only executes the above instruction forever. What would be the maximum clock frequency if the execution times of different units are as given below? Show major steps.
|
I-mem |
Add |
Mux |
ALU |
Registers |
D-Mem |
Sign-extend |
Shift-left-2 |
|
300ps |
100ps |
50ps |
150ps |
80ps |
200ps |
70ps |
20ps |