: A reduced hardware implementation of the classic five stage RISC pipeline might use the EX stagehardware to perform a branch instruction comparison and then not actually deliver the branch target PCto the IF stage until the clock cycle in which the branch instruction reaches the MEM stage. Controlhazard stalls can be reduced by resolving branch instructions in ID, but improving performance in onerespect may reduce performance in other circumstances. How does determining branch outcome in theID stage have the potential to increase data hazard stall cycles?
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